Verilog to VHDL Converter11 APR 2013
You can easily figure out what Verilog to VHDL Converter does by reading its name. It is a small application intended to provide you with a convenient way to convert Verilog code to the VHDL programming language.
Both Verilog and VHDL are hardware description languages that find their practical use in electronic systems and circuit modeling and programming. Verilog to VHDL Converter is a HDL translator that can prove useful for any electronics designers, allowing the accurate translation of Verilog designs to VHDL-compliant standards.
Some of you surely prefer manual conversion to using a dedicated tool and you just might have a point there, since the generated VHDL might not work properly, requiring additional manual rectifications that are meant to guarantee data type compatibility.
The application is built in Java and is capable of processing multiple Verilog files at once. If the input files are in random order, then you must use the 'sort' function prior to proceeding. There are commands for creating exclusion lists, generate one entity or one component exclusively (the ones corresponding to a specified top or module).
Verilog to VHDL Converter can only be run using the command console, but this shouldn't be an inconveninent for those who work with languages such as Verilog and VHDL, experienced enough to handle its simple syntax. The package comes with an example to demonstrate how the conversion is actually performed. An input Verilog file goes through a pre-processing operation (the corresponding RTL file is saved locally) and then the application proceeds to parsing it.
Verilog to VHDL Converter is particularly useful for designers who work in an environment that can handle both languages. Alternatively, it can be integrated into applications that are only compatible with VHDL.
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