Verilog to VHDL Converter 11 APR 2013

Verilog to VHDL Converteris designed as a simple and accessible utility that can be used by those who wants to convert an existing Verilog design into VHDL.

The generated VHDL may not work as is and may require some manual correction to ensure the VHDL data type matching. Verilog to VHDL Converter was developed in the Java programming language and can run on multiple platforms.