Softpedia >Windows >Science / CAD >Proteus PCB Design >  Changelog

Proteus PCB Design Changelog

What's new in Proteus PCB Design 8.9 SP0 Build 27865

May 3, 2019
  • Integrated web search:
  • Version 8.9 sees the completion of the library part import work by introducing a live web search directly into the library pick form. Now, when you search for a part you can move from installed results to web results at the press of a button. Then you simply double click on the web result to import straight into Proteus. Both the schematic component and the PCB footprint will be imported and, in most cases, the 3D STEP file will also be included.
  • There are over 15 million parts in the web search but if the part you want doesn't exist you can request it be built for you. This is a free service and typically takes 24-48 hours. A free account needs to be registered with our partner Samacsys but this can be set up from inside Proteus the first time you try to import a part.
  • Auto-Compete Manual Routing:
  • When routing tracks on the PCB Proteus will now search ahead of the mouse and display a shadow track to a legal destination. You can then simply hit the ENTER button on the keyboard to automatically complete the route as shown by the shadow track. The shadow track will update as you route with the mouse. This allows you to guide the process and then auto-complete when you are happy with the result
  • Panelization:
  • When panelizing, the positioning of the incoming boards often needs to have specific clearances from the panel boundary and between other boards on the panel. We've updated the Gerber Editor so that when you are creating a panel the procedure is now:
  • Set the world area to be the size of your PCB panel.
  • Import your first PCB specifying number of copies and clearances.
  • Repeat if necessary with other PCB's.
  • Draw final board edge around the world area to represent the panel.
  • Cloud Licensing:
  • Following customer requests we've now completed our cloud licensing solution for enterprise customers. This allows the Proteus software to be licensed from a cloud instance. Users will receive a URL and a password, enabling them to log in from their copy of Proteus.
  • System administrators can log in via a secure portal to change the password for access and can also reserve licenses to specific IP addresses, leaving the remaining seats available on a first come, first serve basis. A modest rental surcharge applies annually to cover the costs of the server instance and maintenance. Contact us for details.
  • Miscellaneous:
  • We've also added an importer for EDIF2 schematics and include support for new 8051 variants and a host of embedded peripheral models. More details can be found on the Labcenter support forums.

New in Proteus PCB Design 8.7 SP2 Build 25444 (Feb 8, 2018)

  • We are pleased to announce that Proteus V8.7 is now nearly development complete and we are expecting to release a public Beta shortly. This is a significant release with a focus on simplifying common tasks during PCB Design.
  • High-speed design:
  • With Proteus 8.7 we have continued to improve our support for high speed design, building on the automatic length matching work we started in V8.6. This includes support for complex length matching where one section of track is part of more than one length matched route (as commonly seen with fly-by routing topologies). We’ve also included the ability to add internal lengths to footprints on the layout. This enables more accurate matching for critical signals, particularly with BGA’s where the signal delay inside the chip can be relevant. Finally, we’ve also added navigation and browsing of length matched routes from connectivity highlight mode and reworked the length match report file to contain more information.
  • Automatic via stitching and shielding:
  • Via stitching is a technique used to tie together larger copper areas on different layers, helping keep return paths short and to reduce noise on the PCB. You can automatically stitch planes in Proteus via a simple context menu command. This gives you control over via style and also spacing and row offsets for the stitching pattern. Once placed you can move and edit vias in the normal way. You can remove groups of vias with a selection box and the selection filter or you can remove all stitching vias with the remove stitching command on the zone context menu. A via shield or picket fence can be added around the border of the planes in much the same way. This will create a single row of vias around the perimeter of the zones and can help prevent electromagnetic interference with other equipment. The same technique can be used with high speed routes such as microstrip or stripline to help isolate signals on the PCB operating at different frequencies.
  • Autoplacement and floorplanning:
  • The auto-placer has undergone a major overhaul in Proteus V8.7, allowing auto-placement on both sides of the board and also auto-placement of groups (e.g. power supply) inside placement rooms.
  • You can specify both a placement side and a placement group for all components in the design explorer or via the property assigment tool. On the PCB Layout you can then place room objects and specify which group should be placed inside the room. Placement itself can then be completely automated, limited to a single room or alternatively, you can filter the parts bin by group and then place and wire manually.
  • Library management:
  • Proteus 8.7 also sees the first stage in our roadmap for improved library management tools, particularly for network sharing and multi-user access. In this first iteration we have freshened the GUI in Library Manager and provided onclick part previews for both schematic components and layout footprints. We have also added a diff feature which will highlight both physical differences (e.g. pin change) and also property differences (e.g. stock code change) between selected library parts. Finally, we have expanded the diff feature into a design freshen feature which will cycle through parts on the schematic and layout, comparing them to the latest versions in your libraries and providing a list of changes and differences that you can review and accept/reject. This is intended primarily as an aid to creating new revisions of older projects.
  • IoT Builder:
  • IOTBuilder is a unique prototyping product that can be added to Visual Designer to allow the development of remote user interfaces to Arduino products without writing any code. First design the hardware on schematic by adding electronic shields, sensors and breakout boards via the peripheral gallery. Then use the controls gallery to create the front panel, adding and placing dials, buttons, charts, etc. in the IOTBuilder editor. Finally, use simple Visual Designer flowchart methods to bind the user interface to the electronics. At any time during development the entire system can be tested and debugged in the Proteus VSM simulation. This executes the same compiled HEX file as the real hardware and will also simulate the interaction of the GUI front panel with the electronics. Once everything is working as expected, the firmware and front panel can be deploying to the Arduino Yun™ hardware at the press of a button. The final step is to point the target device at the hardware, watch it acquire the front panel over TCP/IP and then control the remote hardware from your mobile phone, tablet or PC

New in Proteus PCB Design 8.6 SP1 Build 23413 (Feb 7, 2017)

  • Proteus 8.6 is a significant release with a focus on PCB Design automation and includes feature improvements across the entire design workflow. This version involves a file format change which is not backwards compatible with older versions of the software.
  • Context Sensitive help is available on all dialogues via the question mark at the top right of the dialogue forms. Where appropriate, additional reference topics can be found in the main help files accessible from the Help Menu.
  • Layer Stackup and Smart Vias:
  • We have added the ability for a full layer stack to be defined, including the drilling ranges used for vias. This information is then used in board layout to automatically place the correct via when routing. The layer stackup also enables the user to define plane layers which contain no tracking. These layers then become auto-via destinations during routing
  • Assembly Variants:
  • Assembly variants provide a simple way to manage multiple product configurations from a single schematic/pcb project. This is done by specifying the fitted or not fitted status of each component on a per variant basis.
  • Assembly variants are managed in Proteus by the Design Explorer module, which has been completely re-written in Proteus V8.6.
  • Note: Users who import projects from earlier versions of Proteus with parts that have been ‘excluded from BOM’ will see that a variant is automatically created for them with these parts excluded from it. This variant is given a default name (Exc. from BOM) and can be renamed in Design Explorer – Variant Menu.
  • Serpentine Routing / Length Matching:
  • Proteus now includes support for length matching via a simple select and match user interface. Lengths are matched within a specified tolerance and, if vias are used, the lengths of the vias are taken from the layer stackup information. A single configuration dialogue form allows for full control of the serpentine shape and clearance. Users can also adjust either an absolute or a relative tolerance for the match according to the timing budget for the interface.
  • Note: This feature requires PCB Level 2 or higher.
  • Proteus VSM:
  • Proteus 8.6 adds support for STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6, STM32F103T6, PIC16F505, PIC12F508 and PIC12F509 along with numerous new embedded peripheral models.
  • Short Intro movies on the new features can be launched from the Proteus 8 home page

New in Proteus PCB Design 8.5 SP0 Build 22067 (Aug 1, 2016)

  • Gerber X2:
  • Proteus now supports the latest Gerber X2 format along with RS274X
  • Curved Routing:
  • now supported for both Follow Me and Manual routing. This also in cludes improved (i.e. smoother) hug ging of curved tracks within zones.
  • High DPI Support:
  • support is much improved by the introduction of new high quality icons, better fonts, and a number of other issues with high DPI displays have also been fixed.
  • Support for WINDOWS 10 - to go with the high DPI setting support.
  • True Type Font - supported in the 3D Viewer.
  • STEP/IGES Support:
  • Support for MCAD data exchange via STEP and IGES file formats
  • Both import of component STEP/ IGES files and export of the resulting STEP Assembly is supported requires L2 or higher)
  • Includes a large number of supplied STEP files in the libraries
  • Multiple Track Editing:
  • Now includes the ability to edit the width of multiple tracks
  • Now includes the ability to edit the layer of multiple tracks
  • Manually control track necking via the SHIFT button during routing
  • Keepouts:
  • Addition of single layer options for keepout objects
  • New style configuration via standard dialogue UI

New in Proteus PCB Design 8.3 SP0 Build 19725 (Jun 17, 2015)

  • MAIN HIGHLIGHTS:
  • Support for MCAD data exchange via STEP and IGES file formats. Both import of component STEP/IGES files and export of the resulting STEP Assembly is supported (requires L2 or higher).
  • Extensive modifications to existing libraries to include pre-supplied STEP files for radial electrolytics, connectors and some other common parts.
  • Support for multiple track editing operations and enhancements to track necking.
  • Enhanced support for design re-use via sub-circuit binding on the Replicate command.
  • Addition of single layer options for keepout objects (ctx menu command on the keepout object).
  • Enhancement of print sets in ARES to allow paste and soldermask prints alongside copper layers.
  • Significant rework of the PDF output to address various issues with the existing implementation. Also added SVG output.
  • Addition of MSP430G2x variant set.
  • Addition of PIC18F45K50 variant set.
  • Addition of ILI9341 TFT LCD (SPI mode only) and associated Arduino Shield.
  • Addition of many new VSM peripheral models as detailed in the Model Request Forum.

New in Proteus PCB Design 8.2 (Jun 17, 2015)

  • MAIN HIGHLIGHTS:
  • Added new application module for Project Notes. This serves as the documentation center for your work and is fully templated for re-use across projects.
  • New import tool for schematic library parts via the BSDL File format. This is widely supported by silicon vendors and available for most sizeable components.
  • New import tool for PCB footprints via the PADS ASCII layout format. This is fully compatible with both the Lite and Pro PCB Library Expert tools (http://www.pcblibraries.com) as well as via any generic PADS ASCII layout file.
  • Major rework of the Bill of Materials report module to support physical layout configuration and dialogue driven style management.
  • Introduction of Atmel Cortex-M3 variants and new PIC10, PIC16 and PIC18 variants.
  • ALSO ADDED:
  • Proteus VSM for Arduino™:
  • Added Arduino 1.5+ support.
  • Added support for Arduino hardware programming
  • Added SD Card, Ethernet, RTC, LED Bar shields/breakout boards.
  • Updated to correct floating point maths library.
  • ARES:
  • DRC Violations now reported in working units (metric or imperial)
  • Tighten up the shape of the solder resist mask around the corners of rectangular pads.
  • Changed the default guard gap (soldermask) on all Labcenter libraries to be 5th to better reflect modern manufacturing.
  • Added PPC warning where design rules (pad->trace) and guard gap are set such that unwanted exposure of copper features or solder bridges is possible.
  • Maximum zoom level for ARES increased by a factor of 10.
  • Added pre-production check warning for via drill ranges on multi-layer boards being difficult or impossible to manufacture.
  • Pick and Place output now supports metric units in metric mode.
  • Pick and place files no longer contain components excluded from the Bill Of Materials.
  • Layout Zones whose net has been deleted are now treated as ripped to prevent potential unwanted connections to the zone
  • Added an automatic 'move to' option relative to part origin.
  • Added System/Display options command to Gerber Viewer.
  • BOM:
  • BOM title now defaults to project file name if no title has been set
  • Component links in the BOM property editor are now better indicated
  • Page breaks within the BOM are now correctly handled without slicing text
  • The BOM now supports adding external hypertext links to BOM properties.
  • Clearing pending property assignments in the BOM now has a confirmation dialog.
  • You can now easily import and export BOM templates.
  • Several user interface tweaks to the BOM
  • Miscellaneous:
  • Added support for new HTTP based site license server
  • Downloading of updates can now be resumed in case of application exit or other issues during a download.
  • System proxy settings are now supported for downloading data sheets and updates etc.

New in Proteus PCB Design 8.1 (Jun 17, 2015)

  • Main highlights include:
  • Project Clips to enable re-use of blocks of circuitry inside a project or across multiple projects.
  • Enabled suppression of paste mask and solder resist on pad styles and the drawing of custom paste and resist when creating a package. This provides full flexibility when creating library parts.
  • Added support for via-under-smt during routing (FMR mode) and via in pad when making a device (e.g. stitching vias on a thermal pad).
  • Added support for storing external vias in library parts to enable re-use of breakout/fanout tracking on SMT.
  • Added dynamic teardrop control, including a per pad override (Level 2 and higher).
  • Integrated the Arduino toolchain with VSMStudio and added several common Arduino shields (simulation requires license for either Proteus VSM for AVR or Proteus VSM for Arduino).
  • Also added:
  • BOMParts can now be created and edited from within the BOM property view in the same way as normal parts.
  • Added ability to specify custom clearance from pad to zone (e.g. mounting holes)
  • Single layer selection mode now picks up components when layer is Top or Bottom copper enabling selection of SMT components+tracking.
  • Show/hide board option added to 3D visualisation dialogues.
  • Added Layer Usage to New Project Wizard.
  • Enabled Clear Netlist command when netlist errors occur so that subsequent fix-up editing can be done inside the layout.
  • The automatic annotator for the layout is now component side aware, offering additional annotation options.
  • Added PDSPNL file type for panelisation projects.
  • Improved algorithms for maintaining connections when nudging parts a small distance.
  • VSM Studio projects are now built automatically when a simulation is started.
  • Added models for the PIC10(L)F32x processor variants.
  • Added multiple peripheral models across various application areas.
  • Added direct support for Sourceboost and BascomAVR compilers inside VSMStudio.

New in Proteus PCB Design 8.01 SP0 Build 17219 (Dec 4, 2013)

  • Integrated Application Framework:
  • The integrated application framework means that ISIS and ARES are now modules with a single application (PDS.EXE) rather than being separate applications in their own right. They can be run in a single window (tabbed mode) or in two separate 'frames' to give a look and feel similar to that in previous versions. Single frame mode will tend to suit laptop users better whilst multi-frame mode makes the best use of multi-monitor desktop setups.
  • Other features of the software such as Design Explorer, the 3D viewer and maximized graph windows are also presented as top level application modules which again can be held in a single frame or dragged onto another monitor to give a side-by-side view.
  • Common Database:
  • The ISIS and ARES modules share a common database (CDB) which contains information about all the parts and elements in the project. Parts represent the physical components on the PCB whilst elements represent the logical components on the schematic. The CDB also stores the 'binding' between elements and parts. The upshot of all this is that changes to one element (e.g PACKAGE property) of a multi-element part can now be reflected to the other elements automatically whilst changes to the part (in ARES) can be reflected to all the elements. Functions like pinswap, gateswap and back-annotation are much more robust whilst we have also made clearer the effect of changing part IDs (reannotation - all elements get a new part ID) as opposed to element IDs (rebinding - the connectivity is changed) within ISIS.
  • The common database also lays the foundation for a number of powerful features such as design snippets which we plan to bring forth during the lifetime of Proteus 8.
  • Proteus 8 stores the design (DSN), layout (LYT) and common database in a single project file (PDSPRJ) which can also contain a VSM Studio (firmware) project and the associated source code files.
  • Live Netlisting:
  • Proteus 8 maintains a 'live' netlist enabling changes made on the schematic to be reflected in ARES, Design explorer and the Bill Of Materials in real time. Changes to the PCB are shown in such a way that they can still be rejected before components and tracking are actually removed from the layout. A batch mode (live netlisting off) is retained should you prefer to work that way.
  • 3D Viewer:
  • A similar live update mechanism now operates between ARES and the 3D Viewer such that changes to the PCB are auomatically reflected into the 3D view.
  • The rendering code has also been re-written to support both Direct X (as well as Open GL) and also to make it multi-threaded. Render times on machines with 4 or more cores can be more than halved when compared with Proteus 7.
  • Bill of Materials:
  • Proteus 8 includes a completely new Bill of Materials module. This operates in its own application window with a WYSIWYG view of the BOM. Changes to the schematic and/or formatting are reflected immediately and an integrated header/footer editor is also provided.
  • Further more, component properties can be added/removed or edited from within the BOM window. Any changes are automatically back-annotated onto the schematic. This is, of course, the most natural place to add stock/order codes, component costs and so forth.
  • The final output can be to print, HTML or PDF as you wish.
  • VSM Studio:
  • As with ISIS and ARES, the VSM Studio IDE is now an integral part of the single Proteus application.
  • This has the following benefits:
  • Firmware is automatically loaded into the target processor(s) after a successful compile.
  • The new project wizard can both place and wire up basic connections (power, reset etc.) for the chosen target processor
  • Debugging can take place from within *either* the IDE or the schematic.
  • Additionally, Proteus 8 introduces the concept of 'Active Popups'. These are regions of the schematic (e.g. LCD display, or processor pins) that you wish to see whist debugging the code. When debugging in VSM Studio, the Active Popups can be displayed and docked alongside the source code, variables and memory windows. This works especially well on laptops / single monitor setups where managing the popups whilst still being able to see the whole schematic was always something of a challenge.
  • Quality Assurance and Crash Reporting:
  • As always, the Proteus software undergoes intensive testing before release. However, there is always the possibility of unforeseen behaviour causing a software crash. In the event that you do have problems, there is a crash reporting system in place that will prompt you to upload a 'crash dump' to our servers after a successful restart. We would be grateful if as many of you as possible leave this mechanism enabled as the crash dumps will be extremely helpful in understanding why a particular crash occured and where in the software the problem lies.

New in Proteus PCB Design 7.10 (May 29, 2012)

  • Hardware Accelerated Direct2D graphics engine:
  • Lightning fast, flicker free screen redraws.
  • Smooth scrolling and animated object highlighting.
  • Crisp, fully anti-aliased presentation of text and graphics.
  • Current layer is always drawn at the top of the view.
  • User control of layer transparency.
  • Option to display full Solder Resist and Solder Mask layers including shapes contributed by the pad styles.
  • Major overhaul of DXF Importer in ARES to improve support and compatibility with other packages.
  • Dynamic ratsnest during route placement indicates closest net object to track being placed.
  • Automatic dimming of objects during placement helps identify valid route destinations.
  • Improved zone handling to provide more precise clearances for rotated objects.
  • Various smaller user requests including:
  • Ability to specify diagonal ('X') type thermal reliefs on a pad.
  • Visibility of occupancy layer graphics during placement and movement of footprints.
  • Ratsnest lines being shown in their designated colours during component placement and movement.
  • Block selections which include locked objects provide an option to tag all but locked objects before an operation.

New in Proteus PCB Design 7.9 (May 29, 2012)

  • New Follow-Me Routing system in ARES:
  • Fully design rule aware track placement.
  • Designed to follow the path of the mouse from source to destination.
  • Rewind by moving the mouse backwards over existing track during placement.
  • Dropping vias is also design rule aware preventing illegal placement.
  • Floating vias on the end of the track being placed allow precise positioning while obeying board constraints.
  • Pad Style enhancements in ARES:
  • New chamfer and bend radius parameters on through hole DIL pads allowing rounded rectangles or chamfered pads.
  • Design rule system and resist plot generation updated to cater for the new pad topologies.
  • Pads are now allowed to have a specified negative guard gap.
  • 'Move-to' command added for block selection operations on the context menu. This allows absolute positioning of blocks of circuitry and, together with use of the false origin, also allows either for a relative offset of a block.
  • 2D Graphics placement enabled in the gerber viewer, allowing for tab routes during panelisation.
  • Added option to apply text styles to all 2D text on the layout via the Text Styles command on the Technology Menu.
  • Added additional ERC check in ISIS to detect singular net labels. This normally happens when a terminal name has been mistyped.
  • The Pre-Production Checker now includes clickable co-ordinates allowing you to navigate directly to errors on the layout.

New in Proteus PCB Design 7.8 (May 29, 2012)

  • Improved 'follow me' wire routing in ISIS.
  • Layout Technology Files / Technology Menu:
  • These are effectively templates for PCB layout.
  • Board edge, drill holes and other mechanical data may be pre-placed.
  • Design rules, and net-classes may be pre-defined.
  • Grids, start up units, layer usage, and font sizes may be pre-defined.
  • Technology data can been used for new designs and/or applied to existing ones.
  • Colour Sets in ARES:
  • Switch between different visible layers and colours from the View-Layers dialogue.
  • Use a different colour set for printing as opposed to editing.
  • Work with a non-black background colour.
  • Rewritten/improved online Help system.
  • Fully compatible with Windows 7.

New in Proteus PCB Design 7.7 (May 29, 2012)

  • Pre-Production Check detects common design integrity problems prior to Gerber/Excellon or ODB++ output:
  • Unplaced components.
  • Incomplete board edge.
  • Components outside the board edge.
  • Missing or extra connections.
  • Invalid or non-refreshed ground planes.
  • Design rule (DRC Errors)
  • Ability to ignore DRC errors.
  • Support for IDF format export to Circuitworks/Solidworks.
  • Save and restore of default colour settings and other preferences in the 3D viewer.

New in Proteus PCB Design 7.6 (May 29, 2012)

  • Hardware Accelerated / Open GL graphics engine;
  • Lightning fast, flicker free screen redraws.
  • Smooth scrolling and animated object highlighting.
  • Crisp, fully anti-aliased presentation of text and graphics.
  • Current layer is always drawn at the top of the view.
  • User control of layer transparency.
  • Option to display full Solder Resist and Solder Mask layers including shapes contributed by the pad styles.
  • Improved fix-up of connected tracking when a component is moved.
  • Enhanced 3D Viewer display:
  • Hide Components option to give a bare board view.
  • Holes, slots and cut-outs now drawn correctly.
  • Solder resist (and exposed solder) is shown.
  • Bitmaps are shown.
  • STL Export from 3D Viewer - this provides and effective route into solidworks.
  • Adobe PDF Export for both ISIS and ARES.
  • Multi-object alignment commands and move-to (x,y) context command.
  • Over 2000 new library parts including connectors, trimmers and op-amps.

New in Proteus PCB Design 7.5 (May 29, 2012)

  • Improved library search facility including the ability to search by library and stock code, also a filter to show only parts with simulator models. For example, a search of "user res" will show resistors in the user library, whilst a search of "digi res 10k" will show 10k resistors with a digikey stock code.
  • Ability to output library index properties e.g. Manufacturer (MFR), Stock/Order Code (CODE) and Description (DESC) in the Bill of Materials.
  • Dynamic resizing of component libraries.
  • Longer header strings for Author, Revision and Document number.
  • Ability to specify non-default filename for PCB layout.
  • Support for rounded rectangular SMT pads and fiducials in PCB packages.
  • Option for automatic nesting of power plane regions.
  • Better visibility for power plane boundaries.
  • Choice of database, CADCAM and temporary origins in the Goto X/Y command.
  • Dimension display on PCB package previews.
  • Option to print each PCB layer on a separate page.
  • Over 20,000 new real world ISIS library parts (most with Digikey stock codes) and over 2000 IPC7351 PCB footprints.

New in Proteus PCB Design 7.4 (May 29, 2012)

  • Fully integrated Shape Based Auto-Router replaces the previous, grid based router. Users of PCB Design at Level 2 and above can drive the router interactively with the ability to route selected nets. All uses can run a pre-configured routing schedule automatically.
  • Per net 'strategies' are replaced by 'net 'classes', and the management of these is incorporated into the Design Rule Manager.
  • Improved algorithm for device replacement in ISIS.

New in Proteus PCB Design 7.3 (May 29, 2012)

  • Added Support for the ODB++ Unified Manufacturing Output Format.
  • Added Design Rule Manager to ARES, allowing fully customisable board constraints. Includes the ability to set rules by layer and/or by strategy and also to create rules governing behaviour between strategies on the board.
  • Added support for IEEE / North American component symbols to the capacitors and resistors libraries.
  • Fully compatible with Windows Vista.