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This utility takes list of verilog RTL files and the top verilog module name as input and removes all the instances by pulling that's functionality in the top module. You may also consider to explore the flatteninstances tool to flatten specific hierarchical instances. This has been developed in Java( 1.6.x ) in order to make it platform independent.
Usage:
source setup_env ( 'sh' or 'csh' for Unix and '.bat' for Windows DOS Shell )
Alternatively, for Unix
setenv EDAUTILS_ROOT /LinuxShare/WinDataFiles/ProjectRoot/temp/DesignPlayer-linux.x86/01MAY2014
set path = ( $EDAUTILS_ROOT/bin $path )
and for Windows
set EDAUTILS_ROOT=D:\tmp\DesignPlayer-win32.x86_64\01MAY2014
set PATH="%path%;%EDAUTILS_ROOT%\bin"
flatteverilog -in foo.v -top mytop -out flattened.v -hier_delim .
OR
java com.eu.miscedautils.verilogparser.FlattenVerilog -in foo.v -top mytop -out flattened.v -hier_delim .
Where the '.' is the hierarchy delimeter.
Get details of available options by executing it as 'flattenevrilog -help'
Options are as below:
-in <input vlog file> : Mandatory, input verilog file
-top <name-of-module-to-be-flattened> : Mandatory, top module name
-out <output file name > : Optional, output file name
-disble_assgn_merge : Optional, disables assignment merging
-elaborate : Optional, elaborates design
-f <file-containing-list-of-vlog-files> : List of verilog input files
-hier_delim <hierarchy-delimeter-character> : Optional, hierarchy delimeter char, default is '_'
+incdir+<include-path1>+<include-path2> : Optional, compiler directives
-flatten_undefined_modules : Optional, enables flattening of undefined modules as well
-stop_at_leaf : Optional, disables fkattening of leaf module instances
-no_hier : Optional, disables flattening fof hierarchies
-remove_unused_nets : Optional, removes unused nets
-rename_nets : Optional, renames nets to shorter net names
System Verilog RTL Hierarchy Flattener/Ungroup Solution