What's new in Intel Hardware Accelerated Execution Manager 7.8.0

Nov 25, 2022
  • Enabled XSAVE feature in CPUID (#472).
  • Enabled INVPCID instruction (#471).
  • Improved the implementation of CPUID module (#470).
  • Fixed a host crash issue caused by a regression (#469).
  • Improved the user experience of installer (#474).

New in Intel Hardware Accelerated Execution Manager 7.7.1 (Feb 15, 2022)

  • Enhanced the security level of accessing HAX device on Windows
  • Adjusted the coding style of include path for all platforms
  • Cleaned up the legacy VTLB engine

New in Intel Hardware Accelerated Execution Manager 7.7.0 (Jun 2, 2021)

  • Added a new IOCTL to enable getting CPUID features for guest VCPUs (#383).
  • Enabled all supported CPUID leaves to be configurable (#382).
  • Enabled several features in CPUID emulation (#381).
  • Migrated the CI service from Travis CI to GitHub Actions (#353).

New in Intel Hardware Accelerated Execution Manager 7.6.6 (Apr 7, 2021)

  • Optimized the CPUID module and added support for setting two new CPUID leaves (#335).
  • Fixed some vulnerability issues of loading DRs and MSRs (#347).
  • Fixed some minor issues from static code scan (#351).
  • Fixed the download URL in the homepage (#348).

New in Intel Hardware Accelerated Execution Manager 7.6.5 (Sep 17, 2020)

  • Optimized internal storage structure for CPUID feature set (#315).
  • Fixed a performance issue caused by a regression (#312).
  • Fixed some warnings from static code scan (#313).
  • Introduced a new installer framework for Windows.

New in Intel Hardware Accelerated Execution Manager 7.6.1 (Apr 21, 2020)

  • Added a new IOCTL to enable setting CPUID feature for guest VCPUs (#277, #281, #282).
  • Enabled PAT as HAXM supported CPUID feature and added IA32_CR_PAT VMX handling (#204).
  • Changed to return deterministic cache parameters by host cache values (#204).
  • Cleaned up the legacy EPT engine (#261).

New in Intel Hardware Accelerated Execution Manager 7.5.6 (Jan 21, 2020)

  • Enabled support for running on the system with more than 64 host CPUs (#255, #257).
  • Improved the handling of undefined instructions by generating #UD exception (#247).
  • Improved the CPUID features initialization and processing logic (#245).
  • Updated the compilation configurations for Windows and macOS (#243, #244).

New in Intel Hardware Accelerated Execution Manager 7.5.4 (Oct 29, 2019)

  • Change Log:
  • Added VM pause support to fix the crash issue of loading snapshot (#239).
  • Fixed incorrect interruptibility_state to resolve an issue on loading snapshot (#233).
  • Fixed a bug during mapping memory slots (#237).
  • Fixed incorrect VMX_ENTRY_CONTROLS loading (#225).
  • Enabled PCLMULQDQ feature in CPUID emulation if supported by the host (#231).
  • Optimized the log interfaces and enhanced the logging mechanism on Windows (#215, #232).
  • Fixed the compilation warnings and errors on Linux (#223).

New in Intel Hardware Accelerated Execution Manager 7.5.2 (Jul 30, 2019)

  • Added support for ROM devices (#213).
  • Fixed an issue by saving and restoring host flags before and after executing FASTOP instruction (#216).
  • No longer supported dual signing with SHA-1 hashing algorithm for HAXM driver.

New in Intel Hardware Accelerated Execution Manager 7.5.1 (May 24, 2019)

  • Fixed an issue where preparation of a CPU for entry into guest mode could lead to a host kernel panic on NetBSD (#168).
  • Enabled emulation of the CMPS instruction (#176).
  • Improved IA32_EFER virtualization (#188, #198).
  • Added support for stand-alone memory mappings (#197).
  • Enabled emulation of PUSH and POP instructions (#185).
  • Fixed misemulation of instructions that access legacy low-byte registers (#185).

New in Intel Hardware Accelerated Execution Manager 7.4.1 (Feb 2, 2019)

  • Added support for debugging guest code using breakpoints (#66, #81, #114).
  • Enabled/improved emulation of TEST and BT instructions (#104, #122, #135).
  • Added experimental support for Linux and NetBSD hosts (#108, #137).
  • Enabled support for running up to 64 guests simultaneously (#141).
  • Enabled some 32-bit Windows guests to boot under HAXM (#152).
  • Fixed a host crash issue specific to very old Intel CPU models (#101).
  • Fixed a potential Android Emulator hang (#161).
  • Other enhancements and optimizations (#117, #119, #145, etc.).

New in Intel Hardware Accelerated Execution Manager 7.3.2 (Oct 1, 2018)

  • Handle deleted SIP objects.
  • Update paths for UltraVNC and VirtViewer.
  • Indicate if Solar-PuTTY is included or not. Fixes #2595
  • Fix bad link to installation instructions in README.rst. Fixes #2590
  • Downgrade to Qt 5.9. Fixes #2592.

New in Intel Hardware Accelerated Execution Manager 7.3.0 (Aug 14, 2018)

  • Improved memory-mapped I/O (MMIO) handling (#42).
  • Improved host CPU feature detection (#63).
  • Fixed INVEPT errors for macOS and 32-bit Windows hosts (#69, #64).
  • Fixed a BSOD that had affected some Android Emulator users on Windows 10 version 1803 (#68).
  • Fixed a driver signature issue that had prevented some Windows 7 users from installing HAXM (#56).

New in Intel Hardware Accelerated Execution Manager 7.2.0 (May 8, 2018)

  • Enabled experimental support for guest RAM protection, which makes it possible to implement on-demand RAM snapshot loading.
  • Fixed an issue where booting an ISO image in QEMU would lead to a hang (#15).
  • Enabled booting Zircon guests (#7, requires a QEMU-side change).
  • Fixed an issue where certain x86 guests (e.g. Debian Squeeze i386) would fail to boot with a large RAM configuration.
  • Dropped support for macOS 10.9.

New in Intel Hardware Accelerated Execution Manager 7.1.0 (Mar 14, 2018)

  • Updated the virtual CPU model to enable support for the Execute Disable (a.k.a. NX) feature.
  • Improved memory usage tracking logic for future use cases.
  • Added a new IOCTL to support mapping memory regions of 4GB or larger.

New in Intel Hardware Accelerated Execution Manager 7.0.0 (Jan 18, 2018)

  • Added an API to lift the 4GB guest RAM size limitation.
  • Note that a QEMU-side change is required for this feature to take effect.