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RAMMon Changelog

What's new in RAMMon 3.1 Build 1000

Feb 8, 2024
  • 1 Preliminary support for obtaining memory settings for Intel Core chipsets:
  • 2nd gen (Sandy Bridge)
  • 3rd gen (Ivy Bridge)
  • 4th gen (Haswell)
  • 5th gen (Broadwell)
  • 6th gen (Skylake)
  • 7th gen (Kaby lake)
  • 8th gen (Coffee Lake)
  • 9th gen (Coffee Lake Refresh)
  • 10th gen (Comet Lake/Ice Lake)
  • 11th gen (Rocket Lake/Tiger Lake)
  • 12th gen (Alder Lake)
  • 13th gen (Raptor Lake) Core chipsets
  • 2 Preliminary support for obtaining memory settings for Intel Core Ultra chipsets:
  • 1st gen (Meteor Lake)
  • 2nd gen (Arrow Lake)
  • Lunar Lake
  • 3 Preliminary support for obtaining memory settings for Intel Xeon scalable chipsets:
  • 1st gen (Skylake-SP)
  • 2nd gen (Cascade Lake-SP)
  • 3rd gen (Ice Lake-SP)
  • 4th gen (Sapphire Rapids-SP)
  • 5th gen (Emerald Rapids-SP)
  • 4 Preliminary support for obtaining memory settings for Intel Elkhart Lake (Atom X Series) chipsets
  • 5 Fix rounding of DDR5 latency timings
  • 6 Fix driver load issue on Win 10 build 17763 and older
  • 7 Add workaround for BSOD when accessing PCI on Win 10 build 19045 and older

New in RAMMon 3.0 Build 1000 (Dec 21, 2023)

  • Collect and report memory timings, transfer rate, channel mode and other memory settings
  • Collect and report memory/cache size and benchmarks
  • Improve responsiveness on startup by collecting memory information in the background
  • Add button to restart RAMMon in debug mode. Add link to open location of debug log files
  • Check and install Microsoft VC++ Redistributable if required

New in RAMMon 2.5 Build 1000 (Aug 9, 2023)

  • Display additional DDR5 SPD attributes
  • Add workaround for reading DDR5 SPD when SPD write is disabled for Intel chipets
  • Fix DIMM temperature reading issue after reading DDR5 SPD
  • Fix issues with installing DirectIo driver

New in RAMMon 2.4 Build 1000 (Aug 9, 2023)

  • Added support for Intel XMP 3.0 extended SPD timings for DDR5 modules
  • Fixed incorrect reporting of DDR5 module size due to bug in parsing SPD
  • Fixed boot issues on certain AMD Ryzen systems after running RAMMon

New in RAMMon 2.3 Build 1000 (Jan 23, 2023)

  • Added support for DDR5 SPD on AMD Ryzen chipsets
  • Added support for DDR5 SPD on Intel Raptor Lake-S chipsets
  • Fixed buffer overflow when dumping SMBIOS raw bytes in debug log

New in RAMMon 2.2 Build 1000 (Nov 14, 2022)

  • Updated drivers blocked via vulnerable driver blocklist
  • Collect and display DIMM temperatures when available
  • Add 'NOSMBIOS' command line option to disable SMBIOS collection

New in RAMMon 2.1 Build 1000 (Jul 5, 2022)

  • Added DirectIo compatibility for Windows11 22H2

New in RAMMon 2.0 Build 1000 (Mar 11, 2022)

  • Added Support for DDR5 Memory
  • Added Support for On-Die ECC for DDR5

New in RAMMon 1.1 Build 1002 (Sep 16, 2020)

  • Fixed timing issues when accesing Intel SMBus registers
  • Improved check for invalid SPD data
  • Fixed driver security vulnerabilities

New in RAMMon 1.1 Build 1001 (Aug 21, 2018)

  • Fixed Skylake-X (prev. Skylake-E) SMBus not being accessed correctly
  • Added check for invalid SPD revision
  • Added check to prevent hardware registers from being accessed when running from VM

New in RAMMon 1.1 Build 1000 (Feb 7, 2018)

  • Added support for Intel Skylake-E chipsets
  • Fixed DDR4 SPD info not being retrieved for AMD chipsets due to not accessing the upper 256 bytes of the SPD module.
  • Updated JEDEC manufacture ID list
  • Added workaround for crash when Adaptec RAID card is detected when enumerating PCI bus
  • Fixed SMBIOS info not being read for EFI systems due to header not being located in 0xf0000-0xfffff

New in RAMMon 1.0 Build 1016 (Nov 21, 2016)

  • Added support for Intel 5100 SMBus
  • Added support for Intel Sunrise Point SMBus
  • Added support for Intel Broadwell IMC SMBus
  • Added support for Intel Broxton SMBus
  • Added support for Intel Sunrise Point-LP SMBus
  • Added support for Intel Braswell SMBus
  • Fixed SMBus access for AMD Hudson-2/Hudson-3 SMBus
  • Fixed BSOD on some Intel Xeon E5 platforms
  • Fixed SPD collection not working on Intel Xeon E5 platforms with PCI Device 5, Function 0 disabled
  • Added support for temporary disabling of TSOD polling on Intel E5 v3 platforms
  • Improved the speed of collecting SPD data
  • Added "Maximum Activate Window" and "Maximum Activate Count" DDR3 attributes
  • Fixed decoding for DDR3 rev11 timings in SPD
  • Fixed decoding of DDR2 ECC support in SPD
  • Fixed decoding of JEDEC manufacture IDs
  • Added sanity check for invalid characters in the part number string
  • Combined the 32-bit and 64-bit builds into one single package

New in RAMMon 1.0 Build 1015 (Mar 31, 2015)

  • Added support for Intel Wildcat Point PCH
  • Reduced SPD collection time by adding sanity checking of SPD raw data after receiving the first 16 bytes. If bytes are not valid, then the remaining bytes are not retrieved.
  • Changed timeout handling to be more time-sensitive
  • Fixed possible driver crash due to bank address not being restored when retrieving DDR4 SPD
  • Fixed possible buffer overrun due to size of string buffer not being big enough for certain DDR3/DDR4 attributes
  • Fixed SPD info not being retrieved for Sandy Bridge-E/Ivy Bridge-E chipsets when failing to read PCIEx registers from the driver
  • Added force release of ICH SMBus semaphore if unable to acquire. If semaphore release fails, the semaphore bit is ignored.

New in RAMMon 1.0 Build 1014 (Nov 14, 2014)

  • Added support for retrieving SPD parameters from DDR4 modules
  • Added support for Intel XMP 2.0 extended SPD timings for DDR4 modules
  • Added decoding of SPD parameters specific to certain DDR3 module type
  • Fixed SPD decoding of RAM module manufacturer information
  • Added support for Haswell-E chipsets (for DDR4)
  • Added support for Ivy Bridge-EX/Haswell-EX 2nd memory controller
  • Added support for nForce MCP79 secondary SMBus
  • Added handling for Intel ICH's built-in hardware semaphore to prevent SMBus device contention with other threads
  • Corrected a crash bug when decoding DDR3 SPD Module type
  • Fixed crash bug on getting SPD data (if failed to create local mutex)
  • Added checksum verification when searching for SMBIOS header
  • Fixed buffer overrun when parsing end of SMBIOS structure

New in RAMMon 1.0 Build 1013 (May 15, 2014)

  • Fixed program freeze caused by driver lock-up on 32-bit Windows
  • Added support for enabling SMBUS on Intel NM10 Chipsets
  • Increased the maximum number of supported SMBus controllers to 8
  • Fixed SMBUS CLK issues when retrieving SPD details for Intel chipsets

New in RAMMon 1.0 Build 1012 (Feb 5, 2014)

  • Added support for retrieving SPD data for Supermicro server boards that use an SMBus MUX
  • Added support for VIA VT8237S chipset
  • Added support for enabling SMBus on Intel X79 Express Chipset
  • Fixed incorrect decoding of '# of banks' for fully buffered DDR2 RAM causing the DIMM size to be reported incorrectly
  • Increased the number of supported memory modules from 16 to 32
  • Added DDR3 revision 1.3 SPD decoding

New in RAMMon 1.0 Build 1011 (Nov 26, 2013)

  • Improved reliability of retrieving SPD data for Sandy Bridge-E/Ivy Bridge-E chipsets
  • Added support for retrieving SPD data for RAM modules connected to separate CPUs
  • Added support for Intel ValleyView chipset
  • Added support for enabling SMBus on Intel 5 Series chipsets
  • Added support for SMBus enable on SiS96x chipsets

New in RAMMon 1.0 Build 1010 (Oct 3, 2013)

  • Fixed 'Maximum Operating Temperature Range' field
  • Fixed potential conflict when loading DirectIo driver
  • Added support for various newer Intel chipsets
  • Added support for enabling SMBus on various Intel chipsets
  • Added support for various AMD/ATI/nVidia chipsets

New in RAMMon 1.0 Build 1009 (Mar 29, 2013)

  • Fixed bug with displaying incorrect manufacture date
  • Added handling of Intel Sandy Bridge-E variations
  • Fixed bug with nForce MCP55 chipsets
  • Added support for SiS964 chipset
  • Added support for enabling SMBus on Intel 3420 chipsets
  • Added support for enabling SMBus on Intel 82801JB ICH10R chipsets

New in RAMMon 1.0 Build 1008 (Jan 18, 2013)

  • Removed 'Standard Name' and 'Module Name' fields due to variations in supported clock speeds
  • Added 'Transfer Speed' and 'Bandwidth' fields for all clock speeds listed
  • Fixed issue with RAMMon collecting disk SMART info when running in DEBUG mode

New in RAMMon 1.0 Build 1007 (Nov 1, 2012)

  • Fixed 'Standard Name' and 'Module Name' of RAM modules
  • Added SPD detection for Intel Patsburg chipset variations

New in RAMMon 1.0 Build 1006 (Aug 17, 2012)

  • Updated the version of SysInfo in use so it no longer conflicts with other programs using it (eg PerformanceTest 8)
  • Fixed a possible crash (buffer overflow) when displaying the timings at MAX frequency

New in RAMMon 1.0 Build 1005 (Jun 30, 2012)

  • Added SPD detection for Intel 5000x chipsets
  • Added SPD detection for AMD Hudson chipsets
  • Added SPD detection for SIS968 chipsets
  • Fixed decoding of DDR2 FB-DIMM SPD data

New in RAMMon 1.0 Build 1004 (May 15, 2012)

  • Added SPD detection for Intel Patsburg chipsets
  • Fixed decoding of XMP Extreme Profile
  • Reduced SPD retrieval time

New in RAMMon 1.0 Build 1003 (Nov 24, 2011)

  • Added DDR3 SPD version 1.1 detection
  • Fixed HTML report export

New in RAMMon 1.0 Build 1002 (Nov 24, 2011)

  • Added support for XMP extension for DDR3
  • Added support for EPP extension for DDR2

New in RAMMon 1.0 Build 1001 (Nov 24, 2011)

  • Updated SysInfo SDK with newest build 1004
  • Increased debug info saved when DEBUGMODE enabled