Verilog Testbench Generator

Verilog Testbench Generator facilitates the analysis, simulation and testing of a module written using the Verilog hardware description language. To put it another way, it enables circuit creators to test their designs in a secure manner prior to implementation.

As its name implies, this application aims to generate Verilog testbenches that can be put to a test using random input. It comes in handy for creating modelim, ncsim compilations and other types of simulation scripts.

Written using the Java programming language, Verilog Testbench Generator is deployed as a simple JAR file. Before using it, you must go through the environment setup process. To begin with, you must set the EDAUTILS_LICENSE_KEY environment variable. Then, run the ‘setup_env’ file and use the following commands:

set EDAUTILS_ROOT=D: mpDesignPlayer-win32.x86_641MAY2014 ( this installation directory ) set PATH="%path%;%EDAUTILS_ROOT%in"

Once the EDAUTILS root path is set, you can launch the utility using one of the two following commands:

1. gentbvlog -in simple_and.v -top simple_and -out edautils_tech_tb.v [+incdir+dir1+dir2] -clk "clk1@8{in1:in2}" -clk clk2 -rst rst1 -rst "rst2{1@5:0@50:1@150}" 2. java com.eu.miscedautils.gentbvlog.GenTBVlog -in simple_and.v -top simple_and -out edautils_tech_tb.v [+incdir+dir1+dir2] -clk "clk1@8{in1:in2}" -clk clk2 -rest rest1 -rest "rest2{1@5:0@50:1@150}", where: clk is one of the clocks rest2 is the reset.

Verilog Testbench Generator only runs in the command prompt, so prior knowledge of common commands and understanding of the console is required.